The demand for high density and performance associated with ultra large-scale integration semiconductor wiring requires responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped silicon, and a plurality of sequentially formed interlayer dielectrics and interconnected metallization layers defining conductive patterns. An integrated circuit is typically formed of a plurality of conductive patterns including conductive lines separated by interwiring insulator, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns that are positioned on different metallization layers, i.e., upper and lower metallization layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches, which typically extend horizontally with respect to the semiconductor substrate.
A conductive plug filling a via opening is typically formed by depositing an interlayer dielectric on a conductive layer comprising at least one conductive pattern, forming an opening in the interlayer dielectric by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the interlayer dielectric is removed by chemical-mechanical polishing. One such method of forming an interconnect structure is known as damascene and involves forming an opening and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via opening section in communication with an upper trench opening section, and filling the opening with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
High performance microprocessor applications require the rapid speed of semiconductor circuitry. The speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. Tungsten has been used as the interconnect between the devices (FEOL) of a semiconductor and the interconnects (BEOL) for many years. The tungsten is used as a barrier between them so as not to allow any of the BEOL materials to contaminate the FEOL devices thereby rendering them useless.
Copper (Cu) and copper (Cu)-alloys have received considerable attention as a replacement material for tungsten (W) in ultra large-scale interconnection metallization. Copper (Cu) is relatively inexpensive, easy to process, has a lower resistivity than tungsten (W), and has improved electrical properties in comparison to tungsten (W), making copper (Cu) a desirable metal for use as a conductive plug, as well as conductive wiring. However, due to copper's (Cu) diffusion through the inter-dielectric layer, copper (Cu) interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barriers include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium-tungsten (TiW), and silicon nitride (Si3N4). The use of such barrier materials to encapsulate copper (Cu), is not limited to the interface between copper (Cu) and the interlayer dielectric, but includes interfaces with other metals as well.